chipsalliance/

chisel

Chisel: A Modern Hardware Design Language

First-PR friendlyGitHub chisel-lang.org

Start here

Open issues, live

Unassigned, straight from GitHub

Facts

Stars: 4,796
Forks: 659
License: Apache-2.0
Last commit: 11h ago
Replies in: Not measured
Good first issues: 6
Help wanted: 1
Language: Scala
Fields: Embedded & IoT

Topics: #chisel #chisel3 #scala #firrtl #rtl #chip-generator #verilog

Why this score

78

Very welcoming to new contributors, out of 100.

Issues to pick from14/25
6 open good first issues and 1 help wanted
Recent activity20/20
Last commit 11 hours ago
Maintainer replies8/15
Reply time not measured yet, so it counts as average
Onboarding15/15
A CONTRIBUTING guide, a code of conduct and a clear description
Up for grabs15/15
6 of the 6 newest good first issues are unassigned
Reach6/10
4.8K stars, so your work gets seen

First-PR friendly, because it has:

Met: Score of 60 or more
Met: At least 3 good first issues
Met: A CONTRIBUTING guide
Met: Replies within 3 days

Flag this repo (wrong data, not welcoming, gone)